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TPD2E001DRST-NM Datasheet(PDF) 5 Page - Texas Instruments |
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TPD2E001DRST-NM Datasheet(HTML) 5 Page - Texas Instruments |
5 / 21 page 0.1 µF USB Controller R T R T V BUS D+ D– GND GND IO2 D1 IO1 V CC TPD2E001 www.ti.com SLLS684F – JULY 2006 – REVISED FEBRUARY 2012 APPLICATION INFORMATION Detailed Description When placed near the connector, the TPD2E001 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD2E001 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the following layout/ design guidelines should be followed: 1. Place the TPD2E001 solution close to the connector. This allows the TPD2E001 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. 2. Place a 0.1- μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin during the ESD strike event. 3. Make sure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD2E001 consumes nA leakage current. But during the ESD event, VCC and GND may see 15 A to 30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy associated with the ESD strike. 4. Leave the unused IO pins floating. 5. The VCC pin can be connected in two different ways: (a) If the VCC pin is connected to the system power supply, the TPD2E001 works as a transient suppressor for any signal swing above VCC + VF. A 0.1-μF capacitor on the device VCC pin is recommended for ESD bypass. (b) If the VCC pin is not connected to the system power supply, the TPD2E001 can tolerate higher signal swing in the range up to 10 V. Please note that a 0.1- μF capacitor is still recommended at the VCC pin for ESD bypass. Copyright © 2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPD2E001 |
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