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KSZ8873MLLJ Datasheet(PDF) 38 Page - Micrel Semiconductor |
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KSZ8873MLLJ Datasheet(HTML) 38 Page - Micrel Semiconductor |
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38 / 108 page 
Micrel, Inc. KSZ8873MLLJ September 2011 38 M9999-091911-1.8 SPI Slave Serial Bus Configuration In managed mode, the KSZ8873MLLJ can be configured as a SPI slave device. In this mode, a SPI master device (external controller/CPU) has complete programming access to the KSZ8873MLLJ’s 198 registers. Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are indirectly accessed via registers 121 to 131. The KSZ8873MLLJ supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data write. SPI multiple read and multiple write are also supported by the KSZ8873MLLJ to expedite register read back and register configuration, respectively. SPI multiple read is initiated when the master device continues to drive the KSZ8873MLLJ SPISN input pin (SPI Slave Select signal) low after a byte (a register) is read. The KSZ8873MLLJ internal address counter increments automatically to the next byte (next register) after the read. The next byte at the next register address is shifted out onto the KSZ8873MLLJ SPIQ output pin. SPI multiple read continues until the SPI master device terminates it by de-asserting the SPISN signal to the KSZ8873MLLJ. Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8873MLLJ SPISN input pin low after a byte (a register) is written. The KSZ8873MLLJ internal address counter increments automatically to the next byte (next register) after the write. The next byte that is sent from the master device to the KSZ8873MLLJ SDA input pin is written to the next register address. SPI multiple write continues until the SPI master device terminates it by de-asserting the SPISN signal to the KSZ8873MLLJ. For both SPI multiple read and multiple write, the KSZ8873MLLJ internal address counter wraps back to register address zero once the highest register address is reached. This feature allows all 198 KSZ8873MLLJ registers to be read, or written with a single SPI command from any initial register address. The KSZ8873MLLJ is capable of supporting a SPI bus. The following is a sample procedure for programming the KSZ8873MLLJ using the SPI bus: 1. At the board level, connect the KSZ8873MLLJ pins as follows: KSZ8873MLLJ Pin # KSZ8873MLLJ Signal Name External Processor Signal Description 40 SPISN SPI Slave Select 42 SCL (SPIC) SPI Clock 43 SDA (SPID) SPI Data (Master output; Slave input) 39 SPIQ SPI Data (Master input; Slave output) Table 9. SPI Connections 2. Enable SPI slave mode by setting the KSZ8873MLLJ strap-in pins P2LED[1:0] to “10”. 3. Power up the board and assert reset to the KSZ8873MLLJ. 4. Configure the desired register settings in the KSZ8873MLLJ, using the SPI write or multiple write command. 5. Read back and verify the register settings in the KSZ8873MLLJ, using the SPI read or multiple read command. Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down” can be programmed after the switch has been started. The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising edge of SPIC. |
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