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KSZ8873MLLJ Datasheet(PDF) 30 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 30 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
30
M9999-091911-1.8
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data Bits [15:0]
Idle
Read
32 1’s
01
00
1xRRR
RRRRR
Z0
0000_0000_DDDD_DDDD
Z
Write
32 1’s
01
00
0xRRR
RRRRR
10
xxxx_xxxx_DDDD_DDDD
Z
Table 5. Serial Management Interface (SMI) Frame Format
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register
write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit[3] is
undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write operations.
To access the KSZ8873MLLJ registers 0-196 (0x00 – 0xC6), the following applies:
PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address; that is, {PHYAD[2:0], REGAD[4:0]} =
bits [7:0] of the 8-bit address.
TA bits [1:0] are ’Z0’ means the processor MDIO pin is changed to input Hi-Z from output mode and the followed
‘0’ is the read response from device.
TA bits [1:0] are set to ’10’ when write registers.
Registers are 8 data bits wide.
For read operation, data bits [15:8] are read back as 0’s.
For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.


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