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KSZ8873MLLJ Datasheet(PDF) 23 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 23 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
23
M9999-091911-1.8
Table 2. Internal Function Block Status
Normal Operation Mode
This is the default setting bit[1:0]=00 in register 195 after the chip power-up or hardware reset . When KSZ8873MLLJ is in
this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is ready for CPU
read or write.
During the normal operation mode, the host CPU can set the bit[1:0] in register 195 to transit the current normal operation
mode to any one of the other three power management operation modes.
Energy Detect Mode
The energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8873MLLJ is not connected to an active link partner. In this mode, the device will save up to 50% of the power. If the
cable is not plugged, the KSZ8873MLLJ can automatically enter to a low power state, a.k.a., the energy detect mode. In
this mode, KSZ8873MLLJ will keep transmitting 120ns width pulses at 1 pulse/s rate. Once activity resumes due to
plugging a cable or attempting by the far end to establish link, the KSZ8873MLLJ can automatically power up to normal
power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
KSZ8873MLLJ reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The
energy detect mode is entered by setting bit[1:0]=01 in register 195. When the KSZ8873MLLJ is in this mode, it will
monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit[7:0] Go-
Sleep time in register 196, KSZ8873MLLJ will go into a low power state. When KSZ8873MLLJ is in low power state, it will
keep monitoring the cable energy. Once the energy is detected from the cable, KSZ8873MLLJ will enter normal power
state. When KSZ8873MLLJ is at normal power state, it is able to transmit or receive packet from the cable.
It will save about 87% of the power when MII interface is in PHY mode, pin SMTXER3/MII_LINK_3 is connected to High,
register 195 bit [1:0] =01, bit 2 =1(Disable PLL), not cables are connected.
Soft Power Down Mode
The soft power down mode is entered by setting bit[1:0]=10 in register 195. When KSZ8873MLLJ is in this mode, all PLL
clocks are disabled, the PHY and the MAC are off, all internal registers value will not change. When the host set
bit[1:0]=00 in register 195, this device will be back from current soft power down mode to normal operation mode
Power Saving Mode
The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting
bit[1:0]=11 in register 195. When KSZ8873MLLJ is in this mode, all PLL clocks are enabled, MAC is on, all internal
registers value will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls the PHY
transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the
unused receiver block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the
KSZ8873MLLJ can automatically enabled the PHY power up to normal power state from power saving mode.
During this power saving mode, the host CPU can set bit[1:0] =0 in register 195 to transit the current power saving mode
to any one of the other three power management operation modes.
Port based Power Down Mode
In addition, the KSZ8873MLLJ features a per-port power down mode. To save power, a PHY port that is not in use can be
powered down via port control register 29 or 45 bit 3, or MIIM PHY register. It will saves about 15mA per port.
Power Management Operation Modes
KSZ8873MLLJ
Function Blocks
Normal Mode
Power Saving Mode
Energy Detect Mode
Soft Power Down Mode
Internal PLL Clock
Enabled
Enabled
Disabled
Disabled
Tx/Rx PHY
Enabled
Rx unused block disabled Energy detect at Rx
Disabled
MAC
Enabled
Enabled
Disabled
Disabled
Host Interface
Enabled
Enabled
Disabled
Disabled


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