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KSZ8873MLLJ Datasheet(PDF) 14 Page - Micrel Semiconductor

Part # KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

KSZ8873MLLJ Datasheet(HTML) 14 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
14
M9999-091911-1.8
Pin Number
Pin Name
Type
(1)
Description
59
P1LED0
IPU/O
Port 1 LED Indicators:
Default: Link/Act. (refer to register 195 bit[5:4])
Strap option:
Port 3 duplex mode selection(P3DPX)
PU = port 3 to half duplex mode
PD = port 3 to full duplex mode (default)
Note: P1LED0 has weaker internal pull-down, recommend an external pull-
down by a 0.5Kohm resistor.
60
P2LED1
IPU/O
Port 2 LED Indicators:
Default: Speed (refer to register 195 bit[5:4])
Strap option:
Serial bus configuration
Port 2 LED Indicators:
Default: Link/Act. (refer to register 195 bit[5:4])
Strap option
: Serial bus configuration
Serial bus configuration pins to select mode of access to KSZ8873MLLJ
internal registers.
[P2LED1, P2LED0] = [0, 0] — I
2C master (EEPROM) mode
(If EEPROM is not detected, the KSZ8873MLLJ will be configured with the
default values of its internal registers and the values of its strap-in pins.)
Interface Signals
Type
Description
SPIQ
O
Not used (tri-stated)
SCL_MDC
O
I
2C clock
SDA_MDIO
I/O
I
2C data I/O
SPISN
I
Not used
[P2LED1, P2LED0] = [0, 1] — I
2C slave mode
The external I
2C master will drive the SCL_MDC clock.
The KSZ8873MLLJ device addresses are:
1011_1111
<read>
1011_1110
<write>
Interface Signals
Type
Description
SPIQ
O
Not used (tri-stated)
SCL_MDC
I
I
2C clock
SDA_MDIO
I/O
I
2C data I/O
SPISN
I
Not used
[P2LED1, P2LED0] = [1, 0] — SPI slave mode
Interface Signals
Type
Description
SPIQ
O
SPI data out
SCL_MDC
I
SPI clock
SDA_MDIO
I
SPI data In
SPISN
I
SPI chip select
[P2LED1, P2LED0] = [1, 1] – SMI/MIIM-mode
In SMI mode, the KSZ8873MLLJ provides access to all its internal 8-bit
registers through its SCL_MDC and SDA_MDIO pins.
In MIIM mode, the KSZ8873MLLJ provides access to its 16-bit MIIM
registers through its SDC_MDC and SDA_MDIO pins.


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