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KSZ8873MLLJ Datasheet(PDF) 11 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 11 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
11
M9999-091911-1.8
Pin Description and I/O Assignment
Pin Number
Pin Name
Type
(1)
Description
1
RXM1
I/O
Physical receive or transmit signal (– differential)
2
RXP1
I/O
Physical receive or transmit signal (+ differential)
3
AGND
GND
Analog ground
4
TXM1
I/O
Physical transmit or receive signal (– differential)
5
TXP1
I/O
Physical transmit or receive signal (+ differential)
6
VDDA_3.3
P
3.3V analog VDD
7
AGND
GND
Analog ground.
8
ISET
O
Set physical transmit output current.
Pull-down this pin with a 11.8K 1% resistor to ground.
9
VDDA_1.8
P
1.8V analog core power input from VDDCO (pin 56).
10
RXM2
I/O
Physical receive or transmit signal (– differential)
11
RXP2
I/O
Physical receive or transmit signal (+ differential)
12
AGND
GND
Analog ground.
13
TXM2
I/O
Physical transmit or receive signal (– differential)
14
TXP2
I/O
Physical transmit or receive signal (+ differential)
15
FXSD2
I
MLLJ: Floating or connect to analog ground by pull-down resistor.
16
PWRND
IPU
Chip power down input (active low).
17
X1
I
18
X2
O
25 or 50MHz crystal/oscillator clock connections.
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a
3.3V tolerant oscillator and X2 is a no connect.
Note: Clock is +/- 50ppm for both crystal and oscillator, the clock should be
applied to X1 pin before reset voltage goes high.
19
SMTXEN3
I
Switch MII transmit enable
20
SMTXD33/
EN_REFCLKO_3
IPU/I
MLLJ: Switch MII transmit data bit 3
21
SMTXD32/
NC
I
MLLJ: Switch MII transmit data bit 2
22
SMTXD31
I
Switch MII transmit data bit 1
23
SMTXD30
I
Switch MII transmit data bit 0
24
GND
GND
Digital ground
25
VDDIO
P
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well
decoupling capacitors.
26
SMTXC3/
REFCLKI_3
I/O
MLLJ: Switch MII transmit clock (MII modes only)
Output in PHY MII mode and SNI mode
Input in MAC MII.
27
SMTXER3/
MII_LINK_3
IPD
Switch MII transmit error in MII mode
0= MII link indicator from host in MII PHY mode.
1= No link on port 3 MII PHY mode and enable By-pass mode.


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