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KSZ8873MLLJ Datasheet(PDF) 92 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 92 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
92
M9999-091911-1.8
Absolute Maximum Ratings
(1)
Supply Voltage
(VDDA_1.8, VDDC)....................................... –0.5V to 2.4V
(VDDA_3.3V, VDDIO) ................................... –0.5V to 4.0V
Input Voltage ................................................. –0.5V to 4.0V
Output Voltage .............................................. –0.5V to 4.0V
Lead Temperature (soldering, 10sec.)....................... 260°C
Storage Temperature (Ts) ..........................–55°C to 150°C
HBM ESD Rating ...................................................... +/-3KV
Operating Ratings
(2)
Supply Voltage
(VDDA_1.8, VDDC) ............................1.690V to 1.890V
(VDDA_3.3)..........................................2.5V to 3.465V
(VDDIO) ..............................................1.71V to 3.465V
Extended Ambient Temperature (TA)….-40°C to +125°C
Maximum Junction Temperature (TJ Max)………...135°C
Maximum Case Temperature (TC Max)……………150°C
Junction Thermal Resistance
(3)
LQFP (
JA) ............................................... 47.24°C/W
LQFP (
JC)............................................... 19.37°C/W
Electrical Characteristics
(4)
Current consumption is for the single 3.3V supply device only, and includes the 1.8V supply voltages (VDDA, VDDC) that are provided via
power output pin 56(VDDCO).
Each PHY port’s transformer consumes an additional 45mA @ 3.3V for 100BASE-TX and 70mA @ 3.3V for 10BASE-T at fully traffic.
Symbol
Parameter
Condition
Min
Typ
Max
Units
100BASE-TX Operation (All Ports @ 100% Utilization)
Iddxio
100BASE-TX
(analog core + digital core +
transceiver + digital I/O)
VDDA_3.3, VDDIO = 3.3V
Core power is provided from the internal 1.8V
LDO with input voltage VDDIO
115
mA
10BASE-T Operation (All Ports @ 100% Utilization)
Iddxio
10BASE-T
(analog core + digital core +
transceiver + digital I/O)
VDDA_3.3, VDDIO = 3.3V
Core power is provided from the internal 1.8V
LDO with input voltage VDDIO
86
mA
Power Management Mode (with MII in default PHY mode)
Idd3
Power Saving Mode
VDDA_3.3, VDDIO = 3.3V
Unplug Port 1 and Port 2
Set Register 195 bit[1,0] = [1,1]
96
mA
Idd4
Soft Power Down Mode
VDDA_3.3, VDDIO = 3.3V
Set Register 195 bit[1,0] = [1,0]
5
mA
Idd5
Energy Detect Mode
VDDA_3.3, VDDIO = 3.3V
Unplug Port 1 and Port 2
Set Register 195 bit[7,0] = 0x05 with port 3
PHY mode and by-pass mode.
15
mA
TTL Inputs (VDD_IO = 3.3V/2.5V/1.8V)
VIH
Input High Voltage
2.0/2.
0/1.3
V
VIL
Input Low Voltage
0.8/0.
6/0.3
V
IIN
Input Current
VIN = GND ~ VDD_IO
-10
10
µA
TTL Outputs (VDD_IO = 3.3V/2.5V/1.8V)
VOH
Output High Voltage
IOH = -8mA
2.4/1.
9/1.5
V
VOL
Output Low Voltage
IOL = 8mA
0.4/0.
4/0.2
V
|IOZ|
Output Tri-State Leakage
10
µA
100BASE-TX Transmit (measured differentially after 1:1 transformer)
VO
Peak Differential Output Voltage
100Ω termination across differential output
0.95
1.05
V
VIMB
Output Voltage Imbalance
100Ω termination across differential output
2
%


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