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KSZ8873MLLJ Datasheet(PDF) 91 Page - Micrel Semiconductor |
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KSZ8873MLLJ Datasheet(HTML) 91 Page - Micrel Semiconductor |
91 / 108 page ![]() Micrel, Inc. KSZ8873MLLJ September 2011 91 M9999-091911-1.8 Additional MIB Counter Information “Per Port” MIB counters are designed as “read clear.” These counters will be cleared after they are read. “All Port Dropped Packet” MIB counters are not cleared after they are accessed and do not indicate overflow or validity; therefore, the application must keep track of overflow and valid conditions. To read out all the counters, the best performance over the SPI bus is (160+3)*8*200 = 260ms, where there are 160 registers, 3 overheads, 8 clocks per access, at 5MHz. In the heaviest condition, the counters will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds. A high performance SPI master is also recommended to prevent counters overflow. |
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