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KSZ8873MLLJ Datasheet(PDF) 9 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
Download  108 Pages
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 9 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
9
M9999-091911-1.8
List of Figures
Figure 1. Typical Straight Cable Connection ....................................................................................................................... 19
Figure 2. Typical Crossover Cable Connection ................................................................................................................... 20
Figure 3. Auto-Negotiation and Parallel Operation .............................................................................................................. 21
Figure 4. Destination Address Lookup Flow Chart, Stage 1................................................................................................ 25
Figure 5. Destination Address Resolution Flow Chart, Stage 2........................................................................................... 26
Figure 6. 802.1p Priority Field Format ................................................................................................................................. 32
Figure 7. Tail Tag Frame Format ......................................................................................................................................... 34
Figure 8. Tail Tag Rules....................................................................................................................................................... 35
Figure 9. EEPROM Configuration Timing Diagram ............................................................................................................. 37
Figure 10. SPI Write Data Cycle .......................................................................................................................................... 39
Figure 11. SPI Read Data Cycle.......................................................................................................................................... 39
Figure 12. SPI Multiple Write ............................................................................................................................................... 39
Figure 13. SPI Multiple Read ............................................................................................................................................... 40
Figure 14. Far-End Loopback Path...................................................................................................................................... 41
Figure 15. Near-end (Remote) Loopback Path.................................................................................................................... 42
Figure 16. EEPROM Interface Input Timing Diagram.......................................................................................................... 94
Figure 17. EEPROM Interface Output Timing Diagram....................................................................................................... 94
Figure 18. MAC Mode MII Timing – Data Received from MII .............................................................................................. 95
Figure 19. MAC Mode MII Timing – Data Transmitted to MII ............................................................................................. 95
Figure 20. PHY Mode MII Timing – Data Received from MII............................................................................................... 96
Figure 21. PHY Mode MII Timing – Data Transmitted to MII............................................................................................... 96
Figure 22. RMII Timing – Data Received from RMII............................................................................................................ 97
Figure 23. RMII Timing – Data Transmitted to RMII ............................................................................................................ 97
Figure 24. I2C Input Timing.................................................................................................................................................. 98
Figure 25. I2C Start Bit Timing............................................................................................................................................. 98
Figure 26. I2C Stop Bit Timing ............................................................................................................................................. 98
Figure 27. I2C Output Timing............................................................................................................................................... 98
Figure 28. SPI Input Timing ............................................................................................................................................... 100
Figure 29. SPI Output Timing............................................................................................................................................. 101
Figure 30. Auto-Negotiation Timing ................................................................................................................................... 102
Figure 31. MDC/MDIO Timing............................................................................................................................................ 103
Figure 35. 64-Pin LQFP Package ...................................................................................................................................... 108


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