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KSZ8873MLLJ Datasheet(PDF) 8 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 8 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
8
M9999-091911-1.8
Register 184 (0xB8): TXQ Split for Q2 Port 3............................................................................................................ 78
Register 185 (0xB9): TXQ Split for Q1 in Port 3........................................................................................................ 78
Register 186 (0xBA): TXQ Split for Q0 in Port 3 ....................................................................................................... 79
Register 187 (0xBB): Interrupt enable register .......................................................................................................... 80
Register 188 (0xBC): Link Change Interrupt ............................................................................................................. 80
Register 189 (0xBD): Force Pause Off Iteration Limit Enable................................................................................... 80
Register 192 (0xC0): Fiber Signal Threshold ............................................................................................................ 80
Register 193 (0xC1): Internal 1.8V LDO Control ....................................................................................................... 80
Register 194 (0xC2): Insert SRC PVID ..................................................................................................................... 81
Register 195 (0xC3): Power Management and LED Mode ....................................................................................... 82
Register 196(0xC4): Sleep Mode .............................................................................................................................. 83
198 (0xC6): Forward Invalid VID Frame and Host Mode .......................................................................................... 83
Static MAC Address Table ................................................................................................................................................. 84
VLAN Table .......................................................................................................................................................................... 86
Dynamic MAC Address Table ............................................................................................................................................ 87
MIB (Management Information Base) Counters............................................................................................................... 88
Additional MIB Counter Information........................................................................................................................... 91
Absolute Maximum Ratings
(1) ............................................................................................................................................ 92
Operating Ratings
(2) ............................................................................................................................................................ 92
Electrical Characteristics
(4) ................................................................................................................................................ 92
EEPROM Timing .............................................................................................................................................................. 94
MII Timing ......................................................................................................................................................................... 95
RMII Timing....................................................................................................................................................................... 97
I
2C Slave Mode Timing ..................................................................................................................................................... 98
SPI Timing ...................................................................................................................................................................... 100
Auto-Negotiation Timing ................................................................................................................................................. 102
MDC/MDIO Timing ......................................................................................................................................................... 103
Reset Timing................................................................................................................................................................... 104
Reset Circuit ................................................................................................................................................................... 105
Selection of Isolation Transformers................................................................................................................................ 106
Selection of Reference Crystal ........................................................................................................................................ 106
Package Information......................................................................................................................................................... 107


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