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KSZ8873MLLJ Datasheet(PDF) 78 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 78 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
78
M9999-091911-1.8
Register 181 (0xB5): TXQ Split for Q1 in Port 2
Bit
Name
R/W
Description
Default
7
Priority Select
R/W
0 = enable straight priority with Reg 179/180/182 bits[7]=0
and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues
with Reg 179/180/182 bits[7]=1.
1
6:0
Reserved
RO
Reserved
Do not change the default values.
2
Register 182 (0xB6): TXQ Split for Q0 in Port 2
Bit
Name
R/W
Description
Default
7
Priority Select
R/W
0 = enable straight priority with Reg 179/180/181 bits[7]=0
and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues
with Reg 179/180/181 bits[7]=1.
1
6:0
Reserved
RO
Reserved
Do not change the default values.
1
Register 183 (0xB7): TXQ Split for Q3 Port 3
Bit
Name
R/W
Description
Default
7
Priority Select
R/W
0 = enable straight priority with Reg 184/185/186 bits[7]=0
and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues
with Reg 184/185/186 bits[7]=1.
1
6:0
Reserved
RO
Reserved
Do not change the default values.
8
Register 184 (0xB8): TXQ Split for Q2 Port 3
Bit
Name
R/W
Description
Default
7
Priority Select
R/W
0 = enable straight priority with Reg 183/185/186 bits[7]=0
and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues
with Reg 183/185/186 bits[7]=1.
1
6:0
Reserved
RO
Reserved
Do not change the default values.
4
Register 185 (0xB9): TXQ Split for Q1 in Port 3
Bit
Name
R/W
Description
Default
7
Priority Select
R/W
0 = enable straight priority with Reg 183/184/186 bits[7]=0
and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues
with Reg 183/184/186 bits[7]=1.
1
6:0
Reserved
RO
Reserved
Do not change the default values.
2


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