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KSZ8873MLLJ Datasheet(PDF) 75 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
Download  108 Pages
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 75 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
75
M9999-091911-1.8
Bit
Name
R/W
Description
Default
7
Reserved
R/W
Reserved
Do not change the default values.
0
6-0
Q3 Egress
Data Rate limit
R/W
Egress data rate limit for priority 3 frames
Egress traffic from this priority queue is shaped according to
the Data Rate Limit Table.
0
Register 166 (0xA6): KSZ8873 mode indicator
Bit
Name
RO
Description
Default
7-0
KSZ8873
Mode Indicator
RO
bit7: 1: 2 MII mode
bit6: 1: 48P pkg of 2 PHY mode
bit5: 1: Port 1 RMII
0: Port 1 MII
bit4: 1: Port 3 RMII
0: Port 3 MII
bit3: 1: Port 1 MAC MII
0: Port 1 PHY MII
bit2: 1: Port 3 MAC MII
0: Port 3 PHY MII
bit1: 1: Port 1 Copper
0: Port 1 Fiber
bit0: 1: Port 2 Copper
0: Port 2 Fiber
0x03 MLL/MLLJ
0x13 RLL
0x01FLL
Register 167 (0xA7): High Priority Packet Buffer Reserved for Q3
Bit
Name
RW
Description
Default
7-0
Reserved
RO
Reserved
Do not change the default values.
0x45
Register 168 (0xA8): High Priority Packet Buffer Reserved for Q2
Bit
Name
RW
Description
Default
7-0
Reserved
RO
Reserved
Do not change the default values.
0x35
Register 169 (0xA9): High Priority Packet Buffer Reserved for Q1
Bit
Name
RW
Description
Default
7-0
Reserved
RO
Reserved
Do not change the default values.
0x25
Register 170 (0xAA): High Priority Packet Buffer Reserved for Q0
Bit
Name
RW
Description
Default
7-0
Reserved
RO
Reserved
Do not change the default values.
0x15


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