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KSZ8873MLLJ Datasheet(PDF) 74 Page - Micrel Semiconductor

Part # KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

KSZ8873MLLJ Datasheet(HTML) 74 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
74
M9999-091911-1.8
Register 147~142(0x93~0x8E): Station MAC Address 1 MACA1
Register 153~148 (0x99~0x94): Station MAC Address 2 MACA2
Bit
Name
R/W
Description
Default
47-0
Station
address
R/W
48-bit Station address MACA1 and MACA2.
Note: This address is used for self MAC address
filtering, see the port register control 5 bits [6,5]
for detail.
48’h0
Note: the MSB bit[47-40] of the MAC is
the register 147 and 153.
The LSB bit[7-0] of MAC is the register
142 and 148.
Register 154[6:0] (0x9A): Port 1 Q0 Egress data rate limit
Register 158[6:0] (0x9E): Port 2 Q0 Egress data rate limit
Register 162[6:0] (0xA2): Port 3 Q0 Egress data rate limit
Bit
Name
R/W
Description
Default
7
Egress Rate
Limit Flow
Control Enable
R/W
=1, Enable egress rate limit flow control.
=0, Disable
0
6-0
Q0 Egress
Data Rate limit
R/W
Egress data rate limit for priority 0 frames
Egress traffic from this priority queue is shaped according to
the Data Rate Limit Table.
0
Register 155[6:0] (0x9B): Port 1 Q1 Egress data rate limit
Register 159[6:0] (0x9F): Port 2 Q1 Egress data rate limit
Register 163[6:0] (0xA3): Port 3 Q1 Egress data rate limit
Bit
Name
R/W
Description
Default
7
Reserved
R/W
Reserved
Do not change the default values.
0
6-0
Q1 Egress
data Rate limit
R/W
Egress data rate limit for priority 1 frames
Egress traffic from this priority queue is shaped according to
the Data Rate Limit Table.
0
Register 156[6:0] (0x9C): Port 1 Q2 Egress data rate limit
Register 160[6:0] (0xA0): Port 2 Q2 Egress data rate limit
Register 164[6:0] (0xA4): Port 3 Q2 Egress data rate limit
Bit
Name
R/W
Description
Default
7
Reserved
R/W
Reserved
Do not change the default values.
0
6-0
Q2 Egress
Data Rate limit
R/W
Egress data rate limit for priority 2 frames
Egress traffic from this priority queue is shaped according to
the Data Rate Limit Table.
0
Register 157[6:0] (0x9D): Port 1 Q3 Egress data rate limit
Register 161[6:0] (0xA1): Port 2 Q3 Egress data rate limit
Register 165[6:0] (0xA5): Port 3 Q3 Egress data rate limit


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