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KSZ8873MLLJ Datasheet(PDF) 72 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 72 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
72
M9999-091911-1.8
Registers 118 to 120
Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be
used to pass user defined control and status information between the KSZ8873 and the external processor.
Register 118 (0x76): User Defined Register 1
Bit
Name
R/W
Description
Default
7-0
UDR1
R/W
0x00
Register 119 (0x77): User Defined Register 2
Bit
Name
R/W
Description
Default
7-0
UDR2
R/W
0x00
Register 120 (0x78): User Defined Register 3
Bit
Name
R/W
Description
Default
7-0
UDR3
R/W
0x00
Registers 121 to 131
Registers 121 to 131 provide read and write access to the static MAC address table, VLAN table, dynamic MAC address
table, and MIB counters.
Register 121 (0x79): Indirect Access Control 0
Bit
Name
R/W
Description
Default
7-5
Reserved
R/W
Reserved
Do not change the default values.
000
4
Read High /
Write Low
R/W
=1, Read cycle
=0, Write cycle
0
3-2
Table Select
R/W
=00, Static MAC address table selected
=01, VLAN table selected
=10, Dynamic MAC address table selected
=11, MIB counter selected
00
1-0
Indirect
Address High
R/W
Bits [9:8] of indirect address
00
Register 122 (0x7A): Indirect Access Control 1
Bit
Name
R/W
Description
Default
7-0
Indirect
Address Low
R/W
Bits [7:0] of indirect address
0000_0000
Note:
A write to register 122 triggers the read/write command. Read or write access is determined by register 121 bit 4.
Register 123 (0x7B): Indirect Data Register 8
Bit
Name
R/W
Description
Default
7
CPU Read
Status
RO
This bit is applicable only for dynamic MAC address table
and MIB counter reads.
=1, Read is still in progress
=0, Read has completed
0
6-3
Reserved
RO
Reserved
0000
2-0
Indirect Data
[66:64]
RO
Bits [66:64] of indirect data
000


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