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KSZ8873MLLJ Datasheet(PDF) 62 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 62 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
62
M9999-091911-1.8
Register 28 (0x1C): Port 1 Control 12
Register 44 (0x2C): Port 2 Control 12
Register 60 (0x3C): Reserved, not applied to port 3
Bit
Name
R/W
Description
Default
7
Auto
Negotiation
Enable
R/W
=1, Auto negotiation is on
=0, Disable auto negotiation; speed and duplex are
determined by bits 6 and 5 of this register.
1
For port 1, P1ANEN pin value
during reset.
For port 2, SMRXD33 pin
value during reset
6
Force Speed
R/W
=1, Forced 100BT if AN is disabled (bit 7)
=0, Forced 10BT if AN is disabled (bit 7)
1
For port 1, P1SPD pin value
during reset.
For port 2, SMRXD32 pin
value during reset.
5
Force Duplex
R/W
=1, Forced full duplex if (1) AN is disabled or (2) AN is
enabled but failed.
=0, Forced half duplex if (1) AN is disabled or (2) AN is
enabled but failed.
Note: This bit or strap pin should be set to ‘0’ for the correct
duplex mode indication of LED and register status when the
link-up is AN to force mode.
1
For port 1, P1DPX pin value
during reset.
For port 2, SMRXD31 pin
value during reset.
4
Advertise Flow
Control
capability
R/W
=1, Advertise flow control (pause) capability
=0, Suppress flow control (pause) capability from
transmission to link partner
1
3
Advertise
100BT Full
Duplex
Capability
R/W
=1, Advertise 100BT full duplex capability
=0, Suppress 100BT full duplex capability from transmission
to link partner
1
2
Advertise
100BT Half
Duplex
Capability
R/W
=1, Advertise 100BT half duplex capability
=0, Suppress 100BT half duplex capability from
transmission to link partner
1
1
Advertise
10BT Full
Duplex
Capability
R/W
=1, Advertise 10BT full duplex capability
=0, Suppress 10BT full duplex capability from transmission
to link partner
1
0
Advertise
10BT Half
Duplex
Capability
R/W
=1, Advertise 10BT half duplex capability
=0, Suppress 10BT half duplex capability from transmission
to link partner
1
Register 29 (0x1D): Port 1 Control 13
Register 45 (0x2D): Port 2 Control 13
Register 61 (0x3D): Reserved, not applied to port 3
Bit
Name
R/W
Description
Default
7
LED Off
R/W
=1, Turn off all port’s LEDs (LEDx_1, LEDx_0, where “x” is
the port number). These pins will be driven high if this bit is
set to one.
=0, Normal operation
0
6
Txdis
R/W
=1, Disable the port’s transmitter
=0, Normal operation
0


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