 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
KSZ8873MLLJ Datasheet(PDF) 58 Page - Micrel Semiconductor |
|
||||||||||||||||||||||||||||||
KSZ8873MLLJ Datasheet(HTML) 58 Page - Micrel Semiconductor |
|
|
58 / 108 page 
Micrel, Inc. KSZ8873MLLJ September 2011 58 M9999-091911-1.8 Bit Name R/W Description Default (not for 0x35) 4 Drop Ingress Tagged Frame R/W =1, Enable =0, Disable 0 3-2 Limit Mode R/W Ingress Limit Mode These bits determine what kinds of frames are limited and counted against ingress rate limiting. =00, Limit and count all frames =01, Limit and count Broadcast, Multicast, and flooded unicast frames =10, Limit and count Broadcast and Multicast frames only =11, Limit and count Broadcast frames only 00 1 Count IFG R/W Count IFG bytes =1, Each frame’s minimum inter frame gap (IFG) bytes (12 per frame) are included in Ingress and Egress rate limiting calculations. =0, IFG bytes are not counted. 0 0 Count Pre R/W Count Preamble bytes =1, Each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations. =0, Preamble bytes are not counted. 0 Register 22[6:0] (0x16): Port 1 Q0 ingress data rate limit Register 38[6:0] (0x26): Port 2 Q0 ingress data rate limit Register 54[6:0] (0x36): Port 3 Q0 ingress data rate limit Bit Name R/W Description Default 7 RMII REFCLK INVERT R/W =1, Port 3 inverted refclk selected =0, Port 3 original refclk selected Note: Bit 7 is available on port 3 in the RLL device. Other ports and devices will be reserved for this bit. 0 Note: Not Applied to Reg.38(Port 2) 6-0 Q0 Ingress Data Rate limit R/W Ingress data rate limit for priority 0 frames Ingress traffic from this priority queue is shaped according to the ingress Data Rate Limit Table. 0 |
|
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
