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KSZ8873MLLJ Datasheet(PDF) 57 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 57 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
57
M9999-091911-1.8
Bit
Name
R/W
Description
Default
Enable
=0, Disable port’s half duplex back pressure
2
Transmit
Enable
R/W
=1, Enable packet transmission on the port
=0, Disable packet transmission on the port
1
1
Receive
Enable
R/W
=1, Enable packet reception on the port
=0, Disable packet reception on the port
1
0
Learning
Disable
R/W
=1, Disable switch address learning capability
=0, Enable switch address learning
0
Note:
Bits [2:0] are used for spanning tree support.
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Bit
Name
R/W
Description
Default
7-0
Default Tag
[15:8]
R/W
Port’s default tag, containing
7-5 : User priority bits
4 : CFI bit
3-0 : VID[11:8]
0x00
Register 20 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
Bit
Name
R/W
Description
Default
7-0
Default Tag
[7:0]
R/W
Port’s default tag, containing
7-0 : VID[7:0]
0x01
Note: Registers 19 and 20 (and those corresponding to other ports) serve two purposes:
Associated with the ingress untagged packets, and used for egress tagging.
Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.
Register 21 (0x15): Port 1 Control 5
Register 37 (0x25): Port 2 Control 5
Register 53 (0x35): Port 3 Control 5
Bit
Name
R/W
Description
Default
7
Port 3 MII
mode
Selection
R/W
=1, Port 3 MII MAC mode
=0, Port 3 MII PHY mode
Note:
Bit 7 is reserved in the port 1 and port 2 register control 5.
Inversion of power
strapped value of
SMRXDV3.
6
Self-address
filtering
enable
MACA1
(not for
0x35)
R/W
=1, Enable port 1 self-address filtering MACA1
=0, Disable
0
5
Self-address
filtering
enable
MACA2
R/W
=1, Enable port 2 Self-address filtering MACA2
=0, Disable
0


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