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KSZ8873MLLJ Datasheet(PDF) 45 Page - Micrel Semiconductor

Part No. KSZ8873MLLJ
Description  Integrated 3-Port 10/100 Managed Switch with PHYs
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KSZ8873MLLJ Datasheet(HTML) 45 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8873MLLJ
September 2011
45
M9999-091911-1.8
PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status
Bit
Name
R/W
Description
Default
Reference
15
T4 capable
RO
=0, Not 100 BASE-T4 capable
0
14
100 Full
capable
RO
=1, 100BASE-TX full duplex capable
=0, Not capable of 100BASE-TX full duplex
1
Always 1
13
100 Half
capable
RO
=1, 100BASE-TX half duplex capable
=0, Not 100BASE-TX half duplex capable
1
Always 1
12
10 Full
capable
RO
=1, 10BASE-T full duplex capable
=0, Not 10BASE-T full duplex capable
1
Always 1
11
10 Half
capable
RO
=1, 10BASE-T half duplex capable
=0, Not 10BASE-T half duplex capable
1
Always 1
10-7
Reserved
RO
0000
6
Preamble
suppressed
RO
NOT SUPPORTED
0
5
AN complete
RO
=1, Auto-negotiation complete
=0, Auto-negotiation not completed
0
Reg. 30, bit 6
Reg. 46, bit 6
4
Far-end fault
RO
=1, Far-end fault detected
=0, No far-end fault detected
0
Reg. 31, bit 0
3
AN capable
RO
=1, Auto-negotiation capable
=0, Not auto-negotiation capable
1
Reg. 28, bit 7
Reg. 44, bit 7
2
Link status
RO
=1, Link is up
=0, Link is down
0
Reg. 30, bit 5
Reg. 46, bit 5
1
Jabber test
RO
NOT SUPPORTED
0
0
Extended
capable
RO
=0, Not extended register capable
0
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High
Bit
Name
R/W
Description
Default
15-0
PHYID high
RO
High order PHYID bits
0x0022
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low
Bit
Name
R/W
Description
Default
15-0
PHYID low
RO
Low order PHYID bits
0x1430


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