NE555N/NE555D

Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed

pulse whenever the trigger voltage falls below Vcc/3. When the trigger pulse voltage

applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's internal

flip-flop turns the discharging Tr. off and causes the timer output to become high by

charging the external capacitor C1 and setting the flip-flop output at the same time.

The voltage across the external capacitor C1, VC1 increases exponentially with the

When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the

trigger terminal resets the flip-flop, turning the discharging Tr. on. At this time, C1 begins

to discharge and the timer output converts to low.

In this way, the timer operating in the monostable repeats the above process. Figure 2

waveforms during the monostable operation.

It must be noted that, for a normal operation, the trigger pulse voltage needs to

maintain a minimum of Vcc/3 before the timer output turns low. That is, although the

output remains unaffected even if a different trigger pulse is applied while the output is

high, it may be affected and the waveform does not operate properly if the trigger pulse

voltage at the end of the output pulse remains at below Vcc/3. Figure 4 shows such a timer

output abnormality.

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