UCC27423

GND

1

2

3

4

INB

INA

7

6

5

8

OUTA

VDD

OUTB

INPUT

CER

VDD

ENBB

ENBA

2.2

µF

1

µF

UCC27423-Q1

UCC27424-Q1

UCC27425-Q1

SGLS274D

– SEPTEMBER 2008 – REVISED AUGUST 2011

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Parallel Outputs

The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the

OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in

Figure 31.

Figure 31. Parallel Outputs

Operational Waveforms and Circuit Layout

Figure 32 shows the circuit performance achievable with a single driver (half of the 8-pin IC) driving a 10-nF load.

The input pulse width (not shown) is set to 300 ns to show both transitions in the output waveform. Note the

linear rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of

the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.

Figure 32. Pulse Response

In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much

overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high

di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is

advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground on the

opposite side of the output, so the ground should be connected to the bypass capacitors and the load with

copper trace as wide as possible. These connections should also be made with a small enclosed loop area to

minimize the inductance.

16

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