VIN

VIN

PH

VReg

VSENSE

BOOT

OV_TH

COMP

SS

RST_TH

NC

SYNC

LPM

EN

Rslew

NC

Cdly

RT

GND

RST

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

TPS54362-Q1, TPS54362A-Q1

SLVS845D

– MARCH 2009 – REVISED OCTOBER 2011

www.ti.com

DEVICE INFORMATION

PWP 20-PIN PACKAGE

TOP VIEW

PIN FUNCTIONS

PIN

I/O

DESCRIPTION

NAME

NO.

NC

1

NC

Connect to ground

NC

2

NC

Connect to ground

SYNC

3

I

External synchronization clock input to override the internal oscillator clock. An internal pull down

resistor of 62k

Ω (typical) is connected to the ground.

LPM

4

I

Low-power mode control using digital input signal. An internal pull down resistor of 62k

Ω (typical) is

connected to the ground.

EN

5

I

Enable pin, internally pulled up. Must be externally pulled up or down to enable/disable the device.

RT

6

O

External resistor to ground to program the internal oscillator frequency.

Rslew

7

O

External resistor to ground to control the slew rate of internal switching FET.

RST

8

O

Active low, open drain reset output connected to external bias voltage through a resistor, asserted

high after the device starts regulating.

Cdly

9

O

External capacitor to ground to program power on reset delay.

GND

10

O

Ground pin, must be electrically connected to the exposed pad on the PCB for proper thermal

performance.

SS

11

O

External capacitor to ground to program soft start time.

OV_TH

12

I

Sense input for overvoltage detection on regulated output, an external resisitor network is connected

between VReg and ground to program the overvoltage threshold.

RST_TH

13

I

Sense input for overvoltage detection on regulated output, an external resisitor network is connected

between VReg and ground to program the reset and undervoltage threshold.

VSENSE

14

I

Inverting node of error amplifier for voltage mode control

COMP

15

O

Error amplifier output to connect external compensation components.

VReg

16

I

Internal low-side FET to load output during startup or limit overshoot.

PH

17

O

Source of the internal switching FET

VIN

18

I

Unregulated input voltage. Pin 18 and pin 19 must be connected externally.

VIN

19

I

Unregulated input voltage. Pin 18 and pin 19 must be connected externally.

BOOT

20

O

External bootstrap capacitor to PH to drive the gate of the internal switching FET.

6

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Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1