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DS1307 Datasheet(PDF) 9 Page - Tiger Electronic Co.,Ltd

Part No. DS1307
Description  64 X 8 Serial Real Time Clock
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Manufacturer  TGS [Tiger Electronic Co.,Ltd]
Direct Link  http://www.tgselec.com
Logo TGS - Tiger Electronic Co.,Ltd

DS1307 Datasheet(HTML) 9 Page - Tiger Electronic Co.,Ltd

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DS1307
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AC ELECTRICAL CHARACTERISTICS
(0
°C to 70°C or -40°C to +85°C; V
CC =4.5V to 5.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
SCL Clock Frequency
fSCL
0
100
kHz
Bus Free Time Between a STOP and
START Condition
tBUF
4.7
µs
Hold Time (Repeated) START Condition
tHD:STA
4.0
µs
5
LOW Period of SCL Clock
tLOW
4.7
µs
HIGH Period of SCL Clock
tHIGH
4.0
µs
Set-up Time for a Repeated START
Condition
tSU:STA
4.7
µs
Data Hold Time
tHD:DAT
0
µs
6, 7
Data Set-up Time
tSU:DAT
250
ns
Rise Time of Both SDA and SCL Signals
tR
1000
ns
Fall Time of Both SDA and SCL Signals
tF
300
ns
Set-up Time for STOP Condition
tSU:STO
4.7
µs
Capacitive Load for each Bus Line
CB
400
pF
8
I/O Capacitance
CI/O
10
pF
Crystal Specified Load Capacitance
12.5
pF
NOTES:
1.
All voltages are referenced to ground.
2.
Logic zero voltages are specified at a sink current of 5 mA at VCC=4.5V, VOL=GND for capacitive
loads.
3.
ICCS specified with VCC=5.0V and SDA, SCL=5.0V.
4.
VCC=0V, VBAT=3V.
5.
After this period, the first clock pulse is generated.
6.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7.
The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
8.
CB - total capacitance of one bus line in pF.
9.
ICCA - SCL clocking at max frequency = 100 kHz.
10. SCL only.
11. SDA and SQW/OUT


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