Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

DS1307 Datasheet(PDF) 6 Page - Tiger Electronic Co.,Ltd

Part No. DS1307
Description  64 X 8 Serial Real Time Clock
Download  11 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TGS [Tiger Electronic Co.,Ltd]
Direct Link  http://www.tgselec.com
Logo TGS - Tiger Electronic Co.,Ltd

DS1307 Datasheet(HTML) 6 Page - Tiger Electronic Co.,Ltd

Back Button DS1307 Datasheet HTML 2Page - Tiger Electronic Co.,Ltd DS1307 Datasheet HTML 3Page - Tiger Electronic Co.,Ltd DS1307 Datasheet HTML 4Page - Tiger Electronic Co.,Ltd DS1307 Datasheet HTML 5Page - Tiger Electronic Co.,Ltd DS1307 Datasheet HTML 6Page - Tiger Electronic Co.,Ltd DS1307 Datasheet HTML 7Page - Tiger Electronic Co.,Ltd DS1307 Datasheet HTML 8Page - Tiger Electronic Co.,Ltd DS1307 Datasheet HTML 9Page - Tiger Electronic Co.,Ltd DS1307 Datasheet HTML 10Page - Tiger Electronic Co.,Ltd Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 11 page
background image
DS1307
6 of 11
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 5
Depending upon the state of the R/ W bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte. Data is transferred with the most significant bit (MSB) first.
2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave
transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received byte, a ’not acknowledge’ is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred
with the most significant bit (MSB) first.


Html Pages

1  2  3  4  5  6  7  8  9  10  11 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn