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DS1307 Datasheet(PDF) 5 Page - Tiger Electronic Co.,Ltd

Part No. DS1307
Description  64 X 8 Serial Real Time Clock
Download  11 Pages
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Manufacturer  TGS [Tiger Electronic Co.,Ltd]
Direct Link  http://www.tgselec.com
Logo TGS - Tiger Electronic Co.,Ltd

DS1307 Datasheet(HTML) 5 Page - Tiger Electronic Co.,Ltd

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DS1307
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2-WIRE SERIAL DATA BUS
The DS1307 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that
controls the message is called a master. The devices that are controlled by the master are referred to as
slaves. The bus must be controlled by a master device which generates the serial clock (SCL), controls
the bus access, and generates the START and STOP conditions. The DS1307 operates as a slave on the
2-wire bus. A typical bus configuration using this 2-wire protocol is show in Figure 4.
TYPICAL 2-WIRE BUS CONFIGURATION Figure 4
Figures 5, 6, and 7 detail how data is transferred on the 2-wire bus.
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit. Within the 2-wire bus specifications a regular mode (100 kHz clock rate) and a fast mode
(400 kHz clock rate) are defined. The DS1307 operates in the regular mode (100 kHz) only.


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