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DS1302 Datasheet(PDF) 11 Page - Tiger Electronic Co.,Ltd |
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DS1302 Datasheet(HTML) 11 Page - Tiger Electronic Co.,Ltd |
11 / 14 page DS1302 11 of 14 TIMING DIAGRAM: READ DATA TRANSFER Figure 5 TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6 NOTES: 1. All voltages are referenced to ground. 2. Logic one voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at VCC=2.0V, VOH=VCC for capacitive loads. 3. Logic zero voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2.0V, VOL=GND for capacitive loads. 4. ICC1T and ICC2T are specified with I/O open, RST set to a logic “0”, and clock halt flag=0 (oscillator enabled). 5. ICC1A and ICC2A are specified with the I/O pin open, RST high, SCLK=2 MHz at VCC=5V; SCLK=500 kHz, VCC=2.0V and clock halt flag=0 (oscillator enabled). 6. RST , SCLK, and I/O all have 40 kΩ pull–down resistors to ground. 7. Measured at VIH=2.0V or VIL=0.8V and 10 ns maximum rise and fall time. 8. Measured at VOH=2.4V or VOL=0.4V. 9. Load capacitance = 50 pF. 10. ICC1S and ICC2S are specified with RST , I/O, and SCLK open. The clock halt flag must be set to logic one (oscillator disabled). 11. VCC=VCC2, when VCC2>VCC1 +0.2V; VCC=VCC1, when VCC1>VCC2. 12. VCC2=0V. 13. VCC1=0V. 14. Typical values are at 25°C. |
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