© 2011 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN3850T • Rev. 3.0.0

5

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

Time from CLOCK Transition

to Data Becoming Valid

On Falling Edge of CLOCK,

18

43

ns

Time from CLOCK Transition

to Data Becoming Hi-Z

On Rising Edge of CLOCK,

0

5

16

ns

Time from CLOCK Transition

to Data Becoming Valid

On Rising Edge of CLOCK,

18

56

ns

Time from CLOCK Transition

to Data Becoming Hi-Z

On Falling Edge of CLOCK,

0

5

16

ns

Input CLOCK Frequency

(8)

Active Mode

1.0

2.4

4.0

MHz

CLOCK Duty Cycle

(7)

40

50

60

%

Wake-Up Time

(9)

0.35

2.00

ms

(10)

0

0.01

1.00

ms

Load Capacitance on Data

100

pF

Notes:

 

3.

Pseudo-random noise with triangular probability density function. Bandwidth up to 10MHz.

4.

Assumes 120dB(SPL) is mapped to 0Dbfs.

5.

Assumes an input -41, or -38dBV, depending on the part-specific gain.

6.

Verified by design simulation, showing idle tones and low noise level modulation to be typical 96dB.

7.

Guaranteed by characterization.

8.

All parameters are tested at 2.4MHz. Frequency range guaranteed by characterization.

9.

11. Guaranteed by design.

12. Temperature coefficient is calculated by measuring gain in db at 50˚C and -10°C and dividing by 60 (Gain(50°C)

– Gain(-10°C)/60).

Figure 3. Interface Timing