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IDT82V3202NLGBLANK Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT82V3202NLGBLANK Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 117 page  9 September 11, 2009 IDT82V3202 2009 Integrated Device Technology, Inc. DSC-6981/5 EBU WAN PLL IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. FEATURES HIGHLIGHTS • The first single PLL chip: - Features 0.1 Hz to 560 Hz bandwidth - Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements - Provides node clocks for Cellular and WLL base-station (GSM and 3G networks) - Provides clocks for DSL access concentrators (DSLAM), espe- cially for Japan TCM-ISDN network timing based ADSL equip- ments MAIN FEATURES • Provides an integrated single-chip solution for Synchronous Equip- ment Timing Source, including Stratum 3, SMC, 4E and 4 clocks • Employs DPLL and APLL to feature excellent jitter performance and minimize the number of the external components • Supports Forced or Automatic operating mode switch controlled by an internal state machine; the primary operating modes are Free- Run, Locked and Holdover • Supports programmable DPLL bandwidth (0.1 Hz to 560 Hz in 11 steps) and damping factor (1.2 to 20 in 5 steps) • Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy • Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns • Supports phase absorption when phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds • Limits the phase and frequency offset of the outputs • Supports manual and automatic selected input clock switch • Supports automatic hitless selected input clock switch on clock fail- ure • Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing • Provides two 2 kHz, 4 kHz or 8 kHz frame sync input signals, and an 8 kHz frame sync output signal • Provides two input clocks whose frequency cover from 2 kHz to 155.52 MHz • Provides two output clocks whose frequency cover from 1 Hz to 622.08 MHz • Provides output clocks for BITS, GPS, 3G, GSM, etc. • Supports CMOS input/output and PECL/LVDS output technologies • Supports master clock calibration • Supports Line Card application • Meets Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria OTHER FEATURES •I2C programming interface • IEEE 1149.1 JTAG Boundary Scan • Single 3.3 V operation with 5 V tolerant CMOS I/Os • 68-pin VFQFPN package and 64-pin TQFP package, Green pack- age options available APPLICATIONS • BITS / SSU • SMC / SEC (SONET / SDH) • DWDM cross-connect and transmission equipments • Central Office Timing Source and Distribution • Core and access IP switches / routers • Gigabit and Terabit IP switches / routers • IP and ATM core switches and access equipments • Cellular and WLL base-station node clocks • Broadband and multi-service access equipments • Any other telecom equipments that need synchronous equipment system timing |
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