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IDT82V3380A Datasheet(PDF) 78 Page - Integrated Device Technology |
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IDT82V3380A Datasheet(HTML) 78 Page - Integrated Device Technology |
78 / 177 page IDT82V3380A SYNCHRONOUS ETHERNET WAN PLL™ Programming Information 78 May 16, 2011 INTERRUPTS2_STS - Interrupt Status 2 Address: 0EH Type: Read / Write Default Value: 00111111 Bit Name Description 7 T0_OPERATING_MODE This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes. 0: Has not switched. (default) 1: Has switched. This bit is cleared by writing a ‘1’. 6 T0_MAIN_REF_FAILED This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn bit (4AH, 4BH). 0: Has not failed. (default) 1: Has failed. This bit is cleared by writing a ‘1’. 5 - 0 INn This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn for T0 path, i.e., whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn bit (b5~0, 4BH). Here n is any one of 14 to 9. 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a ‘1’. 7 6 54321 0 T0_OPERATING _MODE T0_MAIN_REF_F AILED IN14 IN13 IN12 IN11 IN10 IN9 |
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