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950812YFLFT Datasheet(PDF) 1 Page - Integrated Device Technology |
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950812YFLFT Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 30 page  ICS950812 IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 Frequency Generator with 200MHz Differential CPU Clocks 1 DATASHEET Pin Configuration Recommended Application: CK-408 clock with Buffered/Unbuffered mode supporting Almador, Brookdale, ODEM, and Montara-G chipsets with PIII/ P4 processor. Programmable for group to group skew. Output Features: • 3 0.7V Differential CPU Clock Pairs • 7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks • 3 PCI_F (3.3V) @ 33.3MHz • 1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz • 1 REF (3.3V) @ 14.318MHz • 5 3V66 (3.3V) @ 66.6MHz • 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz • 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz Features: • Provides standard frequencies and additional 5% and 10% over-clocked frequencies • Supports spread spectrum modulation: No spread, Center Spread (±0.35%, ±0.5%, or ±0.75%), or Down Spread (-0.5%, -1.0%, or -1.5%) • Offers adjustable PCI early clock via latch inputs • Selectable 1X or 2X strength for REF via I 2C interface • Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. • Uses external 14.318MHz crystal • Stop clocks and functional control available through I 2C interface. Key Specifications: • CPU Output Jitter <150ps • 3V66 Output Jitter <250ps • 66MHz Output Jitter (Additive) (Buffered Mode) <100ps • CPU Output Skew <100ps Note: Almador board level designs MUST use pin 22, 66MHZ_OUT1, as the feedback connection from the clock buffer path to the Almador (GMCH) chipset. VDDREF 1 56 REF X1 2 55 FS1 X2 3 54 FS0 GND 4 53 CPU_STOP#* PCICLK_F0 5 52 CPUCLKT0 PCICLK_F1 651 CPUCLKC0 PCICLK_F2 7 50 VDDCPU VDDPCI 8 49 CPUCLKT1 GND 9 48 CPUCLKC1 PCICLK0 10 47 GND **E_PCICLK1/PCICLK1 11 46 VDDCPU PCICLK2 12 45 CPUCLKT2 **E_PCICLK3/PCICLK3 13 44 CPUCLKC2 VDDPCI 14 43 MULTSEL* GND 15 42 IREF PCICLK4 16 41 GND PCICLK5 17 40 FS2 PCICLK6 18 39 48MHz_USB/FS3** VDD3V66 19 38 48MHz_DOT GND 20 37 VDD48 66MHZ_OUT0/3V66_2 21 36 GND 66MHZ_OUT1/3V66_3 22 35 3V66_1/VCH_CLK/FS4** 66MHZ_OUT2/3V66_4 23 34 PCI_STOP#* 66MHZ_IN/3V66_5 24 33 3V66_0/FS5** *PD# 25 32 VDD3V66 VDDA 26 31 GND GND 27 30 SCLK Vtt_PWRGD# 28 29 SDATA 56-Pin 300mil SSOP 6.10 mm. Body, 0.50 mm. pitch TSSOP *These inputs have 120K internal pull-up resistors to VDD. **Internal pull-down resistors to ground. Block Diagram PLL2 PLL1 Spread Spectrum 3V66_5/66MHz_IN 3V66_3/66MHz_OUT1 3V66_(4,2)/66MHz_OUT(2,0) 48MHz_USB 48MHz_DOT X1 X2 XTAL OSC 3V66 DIVDER PD# CPU_STOP# PCI_STOP# MULTSEL SDATA SCLK FS (5:0) I REF Control Logic Config. Reg. REF 3V66_0 CPU DIVDER 3 3 CPUCLKT (2:0) CPUCLKC (2:0) Stop 3V66_1/VCH_CLK PCICLK (6:4, 2, 0) PCI DIVDER 3 7 PCICLK_F (2:0) Stop E_PCICLK(1,3)/PCICLK(1,3) 2 VTT_PWRGD# Frequency Select 66MHz_OU T (2:0) 66MHz_IN PCICLK_F 3V66 (4:2) 3V66_5 PCICLK FS2 FS1 FS0 MHz MHz MHz MHz MHz 0 0 0 66.66 66.66 66.66 66.66 33.33 0 0 1 100.00 66.66 66.66 66.66 33.33 0 1 0 200.00 66.66 66.66 66.66 33.33 0 1 1 133.33 66.66 66.66 66.66 33.33 1 0 0 66.66 66.66 66MHz_IN Input 66MHz_IN/2 1 0 1 100.00 66.66 66MHz_IN Input 66MHz_IN/2 1 1 0 200.00 66.66 66MHz_IN Input 66MHz_IN/2 1 1 1 133.33 66.66 66MHz_IN Input 66MHz_IN/2 CPUCLK 3V66 Bit |
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