1602F—11/04/11

ICS9LRS3187B

Programmable Timing Control Hub for Intel Based Systems

11

Datasheet

AC Electrical Characteristics - Low Power Differential Outputs, Commercial Temperature Range

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS Notes

Rising Edge Slew Rate

tSLR

Averaging on

2.5

3.7

4

V/ns

2, 3

Falling Edge Slew Rate

tFLR

Averaging on

2.5

3.7

4

V/ns

2, 3

Slew Rate Variation

tSLVAR

Averaging on

3.6

20

%

1, 6

Differential Voltage Swing

VSWING

Averaging off

300

mV

2

Crossing Point Voltage

VXABS

Averaging off

300

446

550

mV

1,4,5

Crossing Point Variation

VXABSVAR

Averaging off

70

140

mV

1,4,9

Maximum Output Voltage

VHIGH

Averaging off

1150

mV

1,7

Minimum Output Voltage

VLOW

Averaging off

-300

mV

1,8

Duty Cycle

DCYC

Averaging on

45

49.8

55

%

2

CPU Skew

CPUSKEW

Averaging on

35

100

ps

SRC Skew

Averaging on, SRC to SATA skew when Byte0, bit 1 = 0

259

350

ps

Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute

rising meets Clock# falling. The median cross point is used to calculate the voltage

Clock Jitter Specs - Low Power Differential Outputs, Commercial Temperature Range

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS Notes

CPU Jitter - Cycle to Cycle

CPUJC2C

Differential Measurement

50

85

ps

1

SRC/SATA Jitter - Cycle to Cycle

SRCJC2C

Differential Measurement

50

125

ps

1,2

DOT Jitter - Cycle to Cycle

DOTJC2C

Differential Measurement

50

250

ps

1

PCIe Gen 1

35

86

ps (p-

p)

1,2,3

PCIe Gen 2

10kHz < f < 1.5MHz

1.8

3

ps

(RMS)

1,2,3

PCIe Gen 2

1.5MHz < f < Nyquist (50MHz)

2.3

3.1

ps

(RMS)

1,2,3

performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver jitter specs as measured in a real system.

on a component test board under quiet conditions with all outputs on.

SRC Phase Jitter