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9ERS3125BKILF Datasheet(PDF) 2 Page - Integrated Device Technology

Part # 9ERS3125BKILF
Description  Embedded 56-pin Industrial Temperature Range CK505 Compatible Clock
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

9ERS3125BKILF Datasheet(HTML) 2 Page - Integrated Device Technology

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IDTTM/ICSTM
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
1612—08/19/09
ICS9ERS3125
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
2
Datasheet
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
X2
OUT
Crystal output, nominally 14.318MHz.
2
X1
IN
Crystal input, Nominally 14.318MHz.
3
VDDREF
PWR
Power pin for the REF outputs, 3.3V nominal.
4
REF0/FSLC/TEST_SEL
I/O
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-
level latched input to enable test mode. Refer to Test Clarification Table.
5
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
6
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
7
PCI0/CR#_A
I/O
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request
control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock
Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space .
After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request
pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs
address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled.
Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR# A controls SRC2 pair
8
VDDPCI
PWR
Power supply pin for the PCI outputs, 3.3V nominal
9
PCI1/CR#_B
I/O
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request
control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock
Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space .
After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request
pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs
address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled.
Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR# B controls SRC4 pair
10
PCI2/TME
I/O
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on
power-up as follows
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
11
PCI3
OUT
3.3V PCI clock output.
12
PCI4/27_SEL
I/O
3.3V PCI clock output / 27MHz mode select for pin23, 24 strap. On powerup, the logic value
on this pin determines the power-up default of DOT_96/SRC0 and 27MHz/LCD/SRC1 output
and the function table for the pin23 and pin24.
13
PCI_F5/ITP_EN
I/O
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the
state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 45
and 46 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
14
GNDPCI
PWR
Ground for PCI clocks.
15
VDD48
PWR
Power supply for USB clock, nominal 3.3V.
16
USB_48MHz/FSLA
I/O
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer
to input electrical characteristics for Vil_FS and Vih_FS values.
17
GND48
PWR
Ground pin for the 48MHz outputs.
18
VDD96_IO
PWR
Power supply for DOT96 output. 1.05 to 3.3V +/-5%.
19
DOTT_96/SRCT0
OUT
True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin
function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows:
0= SRC0
1=DOT96
20
DOTC_96/SRCC0
OUT
Complement clock of SRC or DOT96. The power-up default function is SRC0#. After
powerup, this pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows
0= SRC0#
1=DOT96#


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