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843001CGI-23 Datasheet(PDF) 8 Page - Integrated Device Technology |
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843001CGI-23 Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 24 page ICS843001CGI-23 REVISION A OCTOBER 4, 2011 8 ©2011 Integrated Device Technology, Inc. ICS843001I-23 Data Sheet FEMTOCLOCK® CRYSTAL/LVCMOS-TO-LVPECL/LVCMOS FREQUENCY SYNTHESIZER Table 6B. AC Characteristics, VCC = 3.3V ± 5%, VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal. NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%. Table 6C. AC Characteristics, VCC = VCCO_LVCMOS = VCCO_LVPECL = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal. NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency Q, nQ 70 637.5 MHz REF_OUT 19.44 27 MHz tPD Propagation Delay; NOTE 1 CLK to REF_OUT 2.3 2.9 ns tjit(Ø) RMS Phase Jitter, (Random); NOTE 2 622.08MHz, (12kHz – 20MHz) 1ps fVCO PLL VCO Lock Range 1.12 1.275 GHz tR / tF Output Rise/Fall Time Q, nQ 20% to 80% 200 700 ps REF_OUT 20% to 80% 350 750 ps odc Output Duty Cycle Q, nQ 46 54 % REF_OUT; NOTE 3 Using Clock Input 48 52 % tLOCK PLL Lock Time 60 ms Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency Q, nQ 70 637.5 MHz REF_OUT 19.44 27 MHz tPD Propagation Delay; NOTE 1 CLK to REF_OUT 2.3 2.9 ns tjit(Ø) RMS Phase Jitter, (Random); NOTE 2 622.08MHz, (12kHz – 20MHz) 1.1 ps fVCO PLL VCO Lock Range 1.12 1.275 GHz tR / tF Output Rise/Fall Time Q, nQ 20% to 80% 200 700 ps REF_OUT 20% to 80% 350 750 ps odc Output Duty Cycle Q, nQ 46 54 % REF_OUT; NOTE 3 Using Clock Input 48 52 % tLOCK PLL Lock Time 60 ms |
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