ICS843001CGI-23 REVISION A OCTOBER 4, 2011

8

©2011 Integrated Device Technology, Inc.

ICS843001I-23 Data Sheet

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.

NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.

NOTE 3: REF_OUT output duty cycle characterized with CLK input duty cycle between 48% and 52%.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

Q, nQ

70

637.5

MHz

REF_OUT

19.44

27

MHz

Propagation Delay;

NOTE 1

CLK to

REF_OUT

2.3

2.9

ns

tjit(Ø)

RMS Phase Jitter, (Random);

NOTE 2

622.08MHz,

(12kHz – 20MHz)

1ps

PLL VCO Lock Range

1.12

1.275

GHz

Output

Rise/Fall Time

Q, nQ

20% to 80%

200

700

ps

REF_OUT

20% to 80%

350

750

ps

odc

Output Duty Cycle

Q, nQ

46

54

%

REF_OUT;

NOTE 3

Using Clock Input

48

52

%

PLL Lock Time

60

ms

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

Q, nQ

70

637.5

MHz

REF_OUT

19.44

27

MHz

Propagation Delay;

NOTE 1

CLK to

REF_OUT

2.3

2.9

ns

tjit(Ø)

RMS Phase Jitter, (Random);

NOTE 2

622.08MHz,

(12kHz – 20MHz)

1.1

ps

PLL VCO Lock Range

1.12

1.275

GHz

Output

Rise/Fall Time

Q, nQ

20% to 80%

200

700

ps

REF_OUT

20% to 80%

350

750

ps

odc

Output Duty Cycle

Q, nQ

46

54

%

REF_OUT;

NOTE 3

Using Clock Input

48

52

%

PLL Lock Time

60

ms