List of Figures

6

December 9, 2011

Figure-1 90E32 Block Diagram .................................................................................................................................................................................... 8

Figure-2 Pin Assignment (Top View) ............................................................................................................................................................................ 9

Figure-3 Energy Register Operation Diagram ............................................................................................................................................................ 14

Figure-4 CFx Pulse Output Regulation ...................................................................................................................................................................... 15

Figure-5 Metering Startup Handling ........................................................................................................................................................................... 16

Figure-6 Block Diagram in Normal Mode ................................................................................................................................................................... 19

Figure-7 Block Diagram in Idle Mode ......................................................................................................................................................................... 20

Figure-8 Block Diagram in Detection Mode ................................................................................................................................................................ 22

Figure-9 Block Diagram in Partial Measurement mode .............................................................................................................................................. 23

Figure-10 Power Mode Transition ............................................................................................................................................................................... 24

Figure-11 Slave Mode ................................................................................................................................................................................................. 26

Figure-12 Read Sequence ........................................................................................................................................................................................... 27

Figure-13 Write Sequence ........................................................................................................................................................................................... 27

Figure-14 IRQ and WarnOut Generation ..................................................................................................................................................................... 37

Figure-15 Current Detection Register Latching Scheme ............................................................................................................................................. 44

Figure-16 Start and Checksum Register Operation Scheme ...................................................................................................................................... 49

Figure-17 SPI Timing Diagram .................................................................................................................................................................................... 65

Figure-18 Power On Reset Timing (90E32 and MCU are Powered on Simultaneously) ............................................................................................ 66

Figure-19 Power On Reset Timing in Normal & Partial Measurement Mode .............................................................................................................. 66

Figure-20 Zero-Crossing Timing Diagram (per phase) ................................................................................................................................................ 67

Figure-21 Voltage Sag and Phase Loss Timing Diagram ............................................................................................................................................ 68

List of Figures