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23S08E-2DCG8 Datasheet(PDF) 3 Page - Integrated Device Technology |
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23S08E-2DCG8 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 11 page 3 COMMERCIALANDINDUSTRIALTEMPERATURERANGES IDT23S08E 3.3V ZERO DELAY CLOCK MULTIPLIER Device FeedbackFrom Bank A Frequency Bank B Frequency IDT23S08E-1 Bank A or Bank B Reference Reference IDT23S08E-1H Bank A or Bank B Reference Reference IDT23S08E-2 Bank A Reference Reference/2 IDT23S08E-2 Bank B 2 x Reference Reference IDT23S08E-2H(1) Bank A Reference Reference/2 IDT23S08E-2H(1) Bank B 2 x Reference Reference IDT23S08E-3(1) Bank A 2 x Reference ReferenceorReference(2) IDT23S08E-3(1) Bank B 4 x Reference 2 x Reference IDT23S08E-4 Bank A or Bank B 2 x Reference 2 x Reference IDT23S08E-5H Bank A or Bank B Reference/2 Reference/2 NOTES: 1. Contact factory for availability. 2. Output phase is indeterminant (0° or 180° from input clock). AVAILABLE OPTIONS FOR IDT23S08 S2 S1 CLK A CLK B Output Source PLL Shut Down L L Tri-State Tri-State PLL Y L H Driven Tri-State PLL N H L Driven Driven REF Y H H Driven Driven PLL N FUNCTION TABLE(1) SELECT INPUT DECODING NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level SPREAD SPECTRUM COMPATIBLE Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization. |
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