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COMMERCIALTEMPERATURERANGE

IDT23S09T

2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE

MAY 2010

2003 Integrated Device Technology, Inc.

DSC 6396/8

c

COMMERCIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five and one bank of

four outputs

• Separate output enable for each output bank

• Output Skew < 250ps

• Low jitter <200 ps cycle-to-cycle

• No external RC network required

• Spread spectrum compatible

• Available in SOIC package

FUNCTIONAL BLOCK DIAGRAM

IDT23S09T

2.5V ZERO DELAY

CLOCK BUFFER, SPREAD

SPECTRUM COMPATIBLE

DESCRIPTION:

The IDT23S09T is a high-speed phase-lock loop (PLL) clock buffer,

designed to address high-speed clock distribution applications. The zero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

The IDT23S09T is a 16-pin version of the IDT23S05T. The IDT23S09T

accepts one reference input, and drives two banks of four low skew clocks.

All parts have on-chip PLLs which lock to an input clock on the REF pin.

The PLL feedback is on-chip and is obtained from the CLKOUT pad. In

the absence of an input clock, the IDT23S09T enters power down, and

the outputs are tri-stated. In this mode, the device will draw less than 12µA.

PLL

S1

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Control

Logic

1

REF

S2

16

CLKOUT

8

9

2

3

14

15

6

7

10

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