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IDT5P49EE602 Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT5P49EE602 Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 25 page IDT5P49EE602 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR 4 IDT5P49EE602 REV C 061110 1) Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL. Alway completely power up VDD and VDDx prior to applying VDDO power. 2) Default configuration CLK1=Buffered MHz Reference output and CLK2=Buffered 32.768kHz output. All other outputs are off. GND 13 Power Connect to Ground. VDD 14 Power Device power supply. Connect to 1.8V. OUT0 15 O Adjustable Configurable clock output 0. Single-ended output voltage levels are register controlled by either VDDO1, VDDO2 or VDDO3. VDDO3 16 Power Device power supply. Connect to 1.8 to 3.3V. Using register settings, select output voltage levels for OUT0/3/6/7/8/9. VDDO3 must be equal or less than VDDO1. SCLK 17 I LVTTL I2C clock. OUT4B 18 O Adjustable Configurable clock output 4B. Single-ended or differential when combined with OUT4A. Output voltage levels are controlled by VDDO1. OUT4A 19 O Adjustable Configurable clock output 4A. Single-ended or differential when combined with OUT4B. Output voltage levels are controlled by VDDO1. SDA 20 I/O Open Drain Bidirectional I2C data. VDD 21 Power Device power supply. Connect to 18.V. GND 22 Power Connect to Ground. XIN/ REF 23 I LVTTL MHz CRYSTAL_IN -- Reference crystal input or external reference clock input. XOUT 24 O LVTTL MHz CRYSTAL_OUT -- Reference crystal feedback. |
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