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9DB403DFLF Datasheet(PDF) 1 Page - Integrated Device Technology |
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9DB403DFLF Datasheet(HTML) 1 Page - Integrated Device Technology |
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ICS9DB403D IDTTM/ICSTM Four Output Differential Buffer for PCIe and Gen 1 and Gen 2 ICS9DB403D REV L 10/07/09 Four Output Differential Buffer for PCIe Gen 1 and Gen 2 DATASHEET 1 Description Output Features The ICS9DB403 is compatible with the Intel DB400v2 Differential Buffer Specification.This buffer provides 4 PCI-Express Gen2 clocks. The ICS9DB403 is driven by a differential output pair from a CK410B+, CK505 or CK509B main clock generator. • 4 - 0.7V current-mode differential output pairs • Supports zero delay buffer mode and fanout mode • Bandwidth programming available • 50-100 MHz operation in PLL mode • 50-400 MHz operation in Bypass mode Functional Block Diagram Key Specifications • Outputs cycle-cycle jitter < 50ps • Outputs skew: 50ps • Phase jitter: PCIe Gen1 < 86ps peak to peak • Phase jitter: PCIe Gen2 < 3.0/3.1ps rms • 28-pin SSOP/TSSOP pacakge • Available in RoHS compliant packaging • Supports Commercial (0 to +70°C) and Industrial (-40 to +85°C) temperature ranges Features/Benefits • Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread. • Supports undriven differential outputs in PD# and SRC_STOP# modes for power management. Note: Polarities shown for OE_INV = 0. STOP LOGIC SRC_IN SRC_IN# DIF(6,5,2,1) CONTROL LOGIC BYPASS#/PLL SDATA SCLK PD SPREAD COMPATIBLE PLL 4 IREF OE(6,5,2,1) 4 M U X -OE(6, 1) 2 |
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