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9DB403DFLF Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. 9DB403DFLF
Description  Four Output Differential Buffer for PCIe Gen 1 and Gen 2
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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9DB403DFLF Datasheet(HTML) 6 Page - Integrated Device Technology

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IDTTM/ICSTM
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
ICS9DB403D
REV L 10/07/09
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
6
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = Tambient for the desired operating range, Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIHSE
2
VDD + 0.3
V1
Input Low Voltage
VILSE
GND - 0.3
0.8
V
1
Input High Current
IIHSE
VIN = VDD
-5
5
uA
1
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
uA
1
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
uA
1
IDD3.3OPC
Full Active, CL = Full load; Commerical
Temp Range
175
200
mA
1
IDD3.3OPI
Full Active, CL = Full load; Industrial Temp
Range
190
225
mA
1
all diff pairs driven, C-Temp
50
60
mA
1
all differential pairs tri-stated, C-Temp
46
mA
1
all diff pairs driven, I-temp
55
65
mA
1
all differential pairs tri-stated, I-temp
68
mA
1
IDD3.3OPC
Full Active, CL = Full load; Commerical
Temp Range
105
125
mA
1
IDD3.3OPI
Full Active, CL = Full load; Industrial Temp
Range
115
150
mA
1
all diff pairs driven, C-Temp
25
30
mA
1
all differential pairs tri-stated, C-Temp
23
mA
1
all diff pairs driven, I-Temp
30
35
mA
1
all differential pairs tri-stated, I-Temp
34
mA
1
FiPLL
PCIe Mode (Bypass#/PLL= 1)
50
100.00
110
MHz
1
FiBYPASS
Bypass Mode ((Bypass#/PLL= 0)
33
400
MHz
1
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs, except SRC_IN
1.5
5
pF
1
CINSRC_IN
SRC_IN differential clock inputs
1.5
2.7
pF
1,4
COUT
Output pin capacitance
6
pF
1
-3dB point in High BW Mode
2
3
4
MHz
1
-3dB point in Low BW Mode
0.7
1
1.4
MHz
1
PLL Jitter Peaking
tJPEAK
Peak Pass band Gain
1.5
2
dB
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st
clock
1ms
1,2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30
33
kHz
1
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1
3
cycles
1,3
Tdrive_SRC_STOP#
tDRVSTP
DIF output enable after
SRC_Stop# de-assertion
10
ns
1,3
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
300
us
1,3
Tfall
tF
Fall time of PD# and SRC_STOP#
5
ns
1
Trise
tR
Rise time of PD# and SRC_STOP#
5
ns
2
SMBus Voltage
VMAX
Maximum input voltage
5.5
V
1
Low-level Output Voltage
VOL
@ IPULLUP
0.4
V
1
Current sinking at VOL
IPULLUP
4mA
1
SCLK/SDATA
Clock/Data Rise Time
tRSMB
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
tFSMB
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
SMBus Operating
Frequency
fMAXSMB
Maximum SMBus operating frequency
100
kHz
1,5
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
IDD3.3PDI
IDD3.3PDI
9DB803 Powerdown
Current
Single Ended Inputs, 3.3 V +/-5%
Input Low Current
IDD3.3PDC
9DB803 Supply Current
9DB403 Supply Current
9DB403 Powerdown
Current
5The differential input clock must be running for the SMBus to be active
Input Frequency
4SRC_IN input
IDD3.3PDC
3Time from deassertion until outputs are >200 mV
PLL Bandwidth
BW
Capacitance


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