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ICS9FG108D Datasheet(PDF) 4 Page - Integrated Device Technology

Part No. ICS9FG108D
Description  Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS9FG108D Datasheet(HTML) 4 Page - Integrated Device Technology

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IDTTM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1542E 12/16/10
ICS9FG108D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
4
Pin Description (continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
25
DIF_STOP#
IN
Active low input to stop differential output clocks.
26
vSPREAD
IN
Asynchronous, active high input to enable spread spectrum functionality. This pin has
a 120Kohm pull down resistor.
27
^SEL14M_25M#
IN
Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm
pull up resistor.
1 = 14.31818 MHz, 0 = 25 MHz
28
vOE_3
IN
Active high input for enabling output 3. This pin has an internal 120kohm pull down
resistor.
0 = tri-state outputs, 1= enable outputs
29
DIF_3#
OUT
0.7V differential Complementary clock output
30
DIF_3
OUT
0.7V differential true clock output
31
VDD
PWR
Power supply, nominal 3.3V
32
DIF_2#
OUT
0.7V differential Complementary clock output
33
DIF_2
OUT
0.7V differential true clock output
34
^OE_2
IN
Active high input for enabling output 2. This pin has in internal 120kohm pull up
resistor.
0 = tri-state outputs, 1= enable outputs
35
GND
PWR
Ground pin.
36
VDD
PWR
Power supply, nominal 3.3V
37
^OE_1
IN
Active high input for enabling output 1. This pin has an internal 120kohm pull up
resistor.
0 = tri-state outputs, 1= enable outputs
38
DIF_1#
OUT
0.7V differential Complementary clock output
39
DIF_1
OUT
0.7V differential true clock output
40
VDD
PWR
Power supply, nominal 3.3V
41
DIF_0#
OUT
0.7V differential Complementary clock output
42
DIF_0
OUT
0.7V differential true clock output
43
vOE_0
IN
Active high input for enabling output 0. This pin has an internal 120kohm pull down
resistor.
0 = tri-state outputs, 1= enable outputs
44
vFS1
IN
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
45
vFS0
IN
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
46
IREF
OUT
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
47
GNDA
PWR
Ground pin for the PLL core.
48
VDDA
PWR
3.3V power for the PLL core.
Note:
^ indicates internal 120K pull up
v indicates internal 120K pull down


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