Four Output Differential Buffer for PCIe Gen 1 and Gen 2

ICS9DB403D

REV L 10/07/09

ICS9DB403D

Four Output Differential Buffer for PCIe for Gen 1 and Gen 2

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The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting

off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the

device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD#

drive mode and Output control bits) before the PLL is shut down.

PD#, Power Down

When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending

on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode

set to ‘1’, both DIF and DIF# are tri-stated.

PD# Assertion

Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from

valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set

to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.

PD# De-assertion

PWRDWN#

DIF

DIF#

PWRDWN#

DIF

DIF#

Tstable

<1mS

Tdrive_PwrDwn#

<300uS, >200mV

Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.