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ICS9DB403D Datasheet(PDF) 3 Page - Integrated Device Technology

Part No. ICS9DB403D
Description  Four Output Differential Buffer for PCIe Gen 1 and Gen 2
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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ICS9DB403D Datasheet(HTML) 3 Page - Integrated Device Technology

 
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IDTTM/ICSTM
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
ICS9DB403D
REV L 10/07/09
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
3
Pin Decription When OE_INV = 0
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
VDD
PWR
Power supply, nominal 3.3V
2
SRC_IN
IN
0.7 V Differential SRC TRUE input
3
SRC_IN#
IN
0.7 V Differential SRC COMPLEMENTARY input
4
GND
PWR
Ground pin.
5
VDD
PWR
Power supply, nominal 3.3V
6
DIF_1
OUT
0.7V differential true clock output
7
DIF_1#
OUT
0.7V differential Complementary clock output
8OE_1
IN
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
9
DIF_2
OUT
0.7V differential true clock output
10
DIF_2#
OUT
0.7V differential Complementary clock output
11
VDD
PWR
Power supply, nominal 3.3V
12
BYPASS#/PLL
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
13
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
14
SDATA
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
15
PD#
IN
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal osc. (if any) are
stopped.
16
DIF_STOP#
IN
Active low input to stop differential output clocks.
17
HIGH_BW#
IN
3.3V input for selecting PLL Band Width
0 = High, 1= Low
18
VDD
PWR
Power supply, nominal 3.3V
19
DIF_5#
OUT
0.7V differential Complementary clock output
20
DIF_5
OUT
0.7V differential true clock output
21
OE_6
IN
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
22
DIF_6#
OUT
0.7V differential Complementary clock output
23
DIF_6
OUT
0.7V differential true clock output
24
VDD
PWR
Power supply, nominal 3.3V
25
OE_INV
IN
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
26
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
27
GNDA
PWR
Ground pin for the PLL core.
28
VDDA
PWR
3.3V power for the PLL core.


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