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ICS9DB403D Datasheet(PDF) 19 Page - Integrated Device Technology

Part No. ICS9DB403D
Description  Four Output Differential Buffer for PCIe Gen 1 and Gen 2
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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ICS9DB403D Datasheet(HTML) 19 Page - Integrated Device Technology

 
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ICS9DB403D
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
19
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks
or registered trademarks used to identify products or services of their respective owners.
Printed in USA
TM
Revision History
Rev.
Issue Date Description
Page #
A
8/15/2006
1. Updated electrical characteristics for final data sheet
2. Corrected references to 8 outputs (should be 4)
-
B
5/22/2007
Updated Polarity Inversion Table.
2
C
1/16/2008
1. Corrected SMBus table to eliminate non-existant outputs. This effects
bytes 1 and 2.
2. Changed PWD notation to Default in SMBus descriptions
11
D
2/29/2008
Added Input Clock Specs
6
E
3/18/2008
Fixed typo in Input Clock Parameters
6
F
4/9/2008
Updated Input Clock Specs
6
G
8/19/2008
Corrected typos on Bytes 1 and 2.
11
H
8/26/2008
1. Updated Electrical Characteristics to add propagation delay and phase
noise information.
2. Corrected SMBus to reference pin numbers for 403 instead of 803 device.
3. Removed references to OE controls that are not present on 403.
4. Added SMBus electrical characteristics
5. Added foot note about DIF input running in order for the SMBus interface
to work
6. Added foot note to Byte 1 about functionality of OE bits and OE pins.
7. Corrected Block Diagram with proper OE pins indicated.
Various
I
11/26/2008 Updated SMBus table - Byte0:Byte3.
11
J
2/6/2009
Added Industrial temp. specs and ordering information.
Various
K
7/13/2009
Updated general description and block diagram
1
L
10/7/2009
1. Clarified that Vih and Vil values were for Single ended inputs
2. Added separate Idd values for the 9DB403
3. Added Differential Clock input parameters.
Various


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