9DB633AGLFT datasheet(9/14 Pages) IDT

Part #	9DB633AGLFT

Description	Six Output Differential Buffer for PCIe Gen3

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Manufacturer	IDT [Integrated Device Technology]

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IDT® Six Output Differential Buffer for PCIe Gen3

1668C—04/20/11

9DB633

Six Output Differential Buffer for PCIe Gen3

9

Datasheet

General SMBus serial interface information for the 9DB633

How to Write:

•

Controller (host) sends a start bit.

• Controller (host) sends the write address D4

(H)

• ICS clock will acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will acknowledge

• Controller (host) starts sending Byte N through

Byte N + X -1

(see Note 2)

• ICS clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D4

(H)

• ICS clock will acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D5

(H)

• ICS clock will acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends Byte N + X -1

• ICS clock sends Byte 0 through byte X (if X

(H)

was written to byte 8).

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Sla ve /Re ce ive r)

T

W R

ACK

P

Byte N + X - 1

Data Byte Count = X

B eginning Byte N

stoP bit

Index Block Write Operation

S lave Address D4(H)

B eginning Byte = N

W Rite

starT bit

Controlle r (Host)

T

starT bit

W R

W Rite

RT

Repeat starT

RD

ReaD

Beginning B yte N

Byte N + X - 1

N

Not acknowledge

P

stoP bit

ICS (Sla ve /Re ce ive r)

Controlle r (Host)

ACK

Data Byte Count = X

ACK

S lave Address D3(H)

Index Block Read Operation

S lave Address D4(H)

B eginning Byte = N

ACK

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