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9DB1904BKLFT Datasheet(PDF) 5 Page - Integrated Device Technology |
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9DB1904BKLFT Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 18 page  IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI 1607C—04/19/11 9DB1904B 19 Output Differential Buffer for PCIe Gen2 and QPI 5 Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES 3.3V Core Supply Voltage VDDA 4.6 V 1,2 3.3V Logic Supply Voltage VDD 4.6 V 1,2 Input Low Voltage VIL GND-0.5 V 1 Input High Voltage VIH Except for SMBus interface VDD+0.5V V 1 Input High Voltage VIHSMB SMBus clock and data pins 5.5V V 1 Storage Temperature Ts -65 150 °C 1 Junction Temperature Tj 125 °C 1 Input ESD protection ESD prot Human Body Model 2000 V 1 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics - Clock Input Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage - DIF_IN VIHDIF Differential inputs (single-ended measurement) 600 800 1150 mV 1 Input Low Voltage - DIF_IN VILDIF Differential inputs (single-ended measurement) VSS - 300 0 300 mV 1 Input Common Mode Voltage - DIF_IN VCOM Common Mode Input Voltage 300 1000 mV 1 Input Amplitude - DIF_IN VSWING Peak to Peak value 300 1450 mV 1 Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2 Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 uA 1 Input Duty Cycle dtin Measurement from differential wavefrom 45 55 % 1, 3 Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 0 125 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. 2Slew rate measured through +/-75mV window centered around differential zero 3 Input duty cycle will directly impact output duty cycle in bypass mode. It has no impact in PLL mode. Electrical Characteristics - Current Consumption TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES IDD3.3OP VDD, All outputs active @100MHz 425 450 mA 1 IDD3.3AOP VDDA, All outputs active @100MHz 35 45 mA 1 IDD3.3PD VDD 20 25 mA 1 IDD3.3APD VDDA 12 15 mA 1 1Guaranteed by design and characterization, not 100% tested in production. Zo = 100Ω Powerdown Current Operating Supply Current |
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