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9DB1233AGLF Datasheet(PDF) 11 Page - Integrated Device Technology |
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9DB1233AGLF Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 15 page IDT® Twelve Output Differential Buffer for PCIe Gen3 9DB1233 Twelve Output Differential Buffer for PCIe Gen3 11 1675B—11/08/10 General SMBus serial interface information for the 9DB1233 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC (h) • IDT clock will acknowledge • Controller (host) sends the begining byte location = N • IDT clock will acknowledge • Controller (host) sends the data byte count = X • IDT clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 • IDT clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address DC (h) • IDT clock will acknowledge • Controller (host) sends the begining byte location = N • IDT clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address DD (h) • IDT clock will acknowledge • IDT clock will send the data byte count = X • IDT clock sends Byte N + X -1 • IDT clock sends Byte 0 through byte X (if X (h) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit IDT (Slave/Receiver) T WR ACK ACK ACK ACK ACK P Byte N + X - 1 Data Byte Count = X Beginning Byte N stoP bit Index Block Write Operation Slave Address DC(h) Beginning Byte = N WRite starT bit Controller (Host) T starT bit WR WRite RT Repeat starT RD ReaD Beginning Byte N Byte N + X - 1 N Not acknowledge P stoP bit IDT (Slave/Receiver) Controller (Host) ACK ACK Data Byte Count = X ACK Slave Address DD(h) Index Block Read Operation Slave Address DC(h) Beginning Byte = N ACK ACK Note: Addresses show assumes pin 29 is low. |
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