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SN65HVD257DR Datasheet(PDF) 5 Page - Texas Instruments |
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SN65HVD257DR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 21 page SN65HVD255 SN65HVD256 www.ti.com SLLSEA2 – DECEMBER 2011 PROTECTION FEATURES TXD DOMINANT TIME OUT (DTO) During normal mode, the only mode where the CAN driver is active, the TXD dominant time out circuit prevents the transceiver from blocking network communication in event of a hardware or software failure where TXD is held dominant longer than the time out period tTXD_DTO. The dominant time out circuit is triggered by a falling edge on TXD. If no rising edge is seen before the time out period of the circuit expires, the CAN bus driver is disabled. This keeps the bus free for communication between other nodes on the network. The CAN driver is re-activated when a recessive signal is seen on TXD pin, thus clearing the TXD dominant time out. The receiver and RXD pin will still reflect the CAN bus and the bus pins will be biased to recessive level during a TXD dominant time out. APPLICATION NOTE: The minimum dominant TXD time allowed by the TXD dominant time out limits the minimum possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate. The minimum transmitted data rate may be calculated by: Minimum Data Rate = 11/ tTXD_DTO. THERMAL SHUTDOWN If the junction temperature of the device exceeds the thermal shut down threshold the device will turn off the CAN driver circuits thus blocking the TXD to bus transmission path. The shutdown condition is cleared once the junction temperature drops below the thermal shutdown temperature of the device. APPLICATION NOTE: During thermal shutdown the CAN bus drivers will be turned off thus no transmission is possible from TXD to the bus. The CAN bus pins will be biased to recessive level during a thermal shutdown and the receiver to RXD path will remain operational. UNDER VOLTAGE LOCKOUT The supply pins have undervoltage detection which place the device in protected mode. This protects the bus during an undervoltage event on either the VCC or VRXD supply pins. Table 4. Undervoltage Lockout 5V Only Device VCC DEVICE STATE BUS OUTPUT RXD GOOD Normal Per Device State and TXD Mirrors Bus BAD Protected High Impedance High Impedance (3-state) Table 5. Undervoltage Lockout 5V and VRXD Device VCC VRXD DEVICE STATE BUS OUTPUT RXD GOOD GOOD Normal Per Device State and TXD Mirrors Bus BAD GOOD Protected High Impedance High (Recessive) GOOD BAD Protected Recessive High Impedance (3-state) BAD BAD Protected High Impedance High Impedance (3-state) APPLICATION NOTE: Once an undervoltage condition is cleared and the supplies have returned to valid levels the device will typically need 300 µs to transition to normal operation. UNPOWERED DEVICE The device is designed to be an "ideal passive" or “no load” to the CAN bus if it is unpowered. The bus pins (CANH, CANL) have extremely low leakage currents when the device is unpowered so they will not load down the bus. This is critical if some nodes of the network will be unpowered while the rest of the of network remains in operation. Logic pins will also have extremely low leakage currents when the device is unpowered so they will not load down other circuits which may remain powered. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): SN65HVD255 SN65HVD256 |
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