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DRV612 Datasheet(PDF) 11 Page - Texas Instruments |
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DRV612 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 23 page fc IN + 1 2p R IN CIN C IN + 1 2p fc IN RIN or Supply ramp Supply MUTE _ Time for ac -coupling capasitors to charge DRV612 www.ti.com SLOS690B – DECEMBER 2010 – REVISED APRIL 2011 Input-Blocking Capacitors DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the DRV612. These capacitors block the dc portion of the audio source and allow the DRV612 inputs to be properly biased to provide maximum performance. The input blocking capacitors also limit the dc gain to 1, limiting the dc-offset voltage at the output. These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the input resistor chosen from Table 2. Then the frequency and/or capacitance can be determined when one of the two values is given. (1) For a fixed cutoff frequency of 2 Hz, the size of the input capacitance is shown in Table 2 with the capacitors rounded up to nearest E6 values. For 20-Hz cutoff, simply divide the capacitor values with 10; e.g., for 1 × gain, 150 nF is needed. Table 2. Input Capacitor for Different Gain and Cutoff Gain_set Gain INPUT 2 Hz GAIN RESISTOR (dB) RESISTANCE Cutoff 249 k Ω –2 × 6 37 k Ω 2.2 µF 82k5 –1 × 0.0 55 k Ω 1.5 µF 51k1 –1.5× 3.5 44 k Ω 2.2 µF 34k8 –2.3× 7.2 33 k Ω 3.3 µF 27k4 –2.5× 8 31 k Ω 3.3 µF 20k5 –3× 9.5 28 k Ω 3.3 µF 15k4 –3.5× 10.9 24 k Ω 3.3 µF 11k5 –4× 12 22 k Ω 4.7 µF 9k09 –5× 14 18 k Ω 4.7 µF 7k5 –5.6× 15 17 k Ω 4.7 µF 6k19 –6.4× 16.1 15 k Ω 6.8 µF 5k11 –8.3× 18.4 12 k Ω 6.8 µF 4k22 –10× 20 10 k Ω 10 µF Pop-Free Power Up Pop-free power up is ensured by keeping the MUTE pin low during power-supply ramp-up and -down. The pins should be kept low until the input ac-coupling capacitors are fully charged before asserting the MUTE pin high, this way proper pre-charge of the ac-coupling is performed and pop-less power up is achieved. Figure 9 illustrates the preferred sequence. Figure 9. Power-Up/Down Sequence Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s) :DRV612 |
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