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PSMN8R0-30YL Datasheet(PDF) 6 Page - NXP Semiconductors |
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PSMN8R0-30YL Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 14 page PSMN8R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 16 May 2011 6 of 14 NXP Semiconductors PSMN8R0-30YL N-channel 8.3 m Ω 30 V TrenchMOS logic level FET in LFPAK Source-drain diode VSD source-drain voltage IS =25A; VGS =0V; Tj =25°C; see Figure 16 -0.9 1.2 V trr reverse recovery time IS =15A; dIS/dt = -100 A/µs; VGS =0V; VDS =15V -34 - ns Qr recovered charge - 30 - nC Table 6. Characteristics …continued Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 7. Forward transconductance as a function of drain current; typical values Fig 8. Input and reverse transfer capacitances as a function of gate-source voltage; typical values 003aaf421 0 20 40 60 80 0 0.5 1 1.5 2 VDS(V) ID (A) 2.4 VGS(V) = 10 2.6 2.8 3.0 3.5 4.5 003aaf422 0 15 30 45 60 01 23 45 VGS(V) ID (A) Tj = 25 °C Tj = 150 °C 003aaf423 0 15 30 45 60 015 30 45 60 ID (A) gfs (S) 003aaf424 0 500 1000 1500 2000 0369 12 VGS(V) C (pF) Ciss Crss |
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