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W9412G2IB Datasheet(PDF) 13 Page - Winbond

Part # W9412G2IB
Description  1M 횞 4 BANKS 횞 32 BITS GDDR SDRAM
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W9412G2IB Datasheet(HTML) 13 Page - Winbond

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W9412G2IB
Publication Release Date: Aug. 30, 2010
- 13 -
Revision A06
The refresh addressing is generated by the internal refresh controller. This makes the address
bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO RE-
FRESH cycles at an average periodic interval of tREFI (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be
posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO
REFRESH command and the next AUTO REFRESH command is 8 * tREFI.
7.2.14
Self Refresh Entry Command
( RAS = “L”, CAS = “L”, WE = “H”, CKE = “L”, BA0, BA1, A0 to A11 = Don’t Care)
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of
the system is powered down. When in the self refresh mode, the DDR SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF
REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is
enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command
can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is
an SSTL_2 input, VREF must be maintained during SELF REFRESH.
7.2.15
Self Refresh Exit Command
(CKE = “H”, CS = “H” or CKE = “H”, RAS = “H”, CAS = “H”)
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be
stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP
commands issued for tXSNR because time is required for the completion of any internal refresh in
progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for
200 clock cycles before applying any other command.
The use of SELF REFREH mode introduces the possibility that an internally timed event can be
missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an
extra auto refresh command is recommended.
7.2.16
Data Write Enable /Disable Command
(DM = “L/H” or DM0
−DM3 = “L/H”)
During a Write cycle, the DM0
−DM3, DMs signal functions as Data Mask and can control every
word of the input data. The DM0 signal controls DQ0 to DQ7, DM1 signal controls DQ8 to DQ15,
DM2 signal controls DQ16 to DQ23 and DM3 signal controls DQ24 to DQ31.
7.3 Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read
command is issued after tRCD from the Bank Activate command, the data is read out sequentially,
synchronized with both edges of DQS (Burst Read operation). The initial read data becomes
available after CAS Latency from the issuing of the Read command. The CAS Latency must be set
in the Mode Register at power-up.
When the Precharge Operation is performed on a bank during a Burst Read and operation, the
Burst operation is terminated.
When the Read with Auto-precharge command is issued, the Precharge operation is performed
automatically after the Read cycle, then the bank is switched to the idle state. This command
cannot be interrupted by any other commands. Refer to the diagrams for Read operation.


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