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W9412G2IB Datasheet(PDF) 7 Page - Winbond

Part # W9412G2IB
Description  1M 횞 4 BANKS 횞 32 BITS GDDR SDRAM
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W9412G2IB Datasheet(HTML) 7 Page - Winbond

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W9412G2IB
Publication Release Date: Aug. 30, 2010
- 7 -
Revision A06
5. BALL DESCRIPTION
BALL LOCATION PIN NAME
FUNCTION
DESCRIPTION
M4-M10, L5-L8, K5
A0
−A11
Address
Multiplexed pins for row and column address.
Row
address: A0
−A11. Column address: A0−A7. (A8 is used
for Auto-precharge)
M3, L4
BA0, BA1
Bank Address
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
A4-A9,B1,B5,B8,
B12,C1,C2,C11,C1
2,D1,D12,E1,E2,E1
1,E12,F1,F2,F11,F1
2,H1,H2,H11,H12,J
1,J2,J11,J12
DQ0
−DQ31 Data Input/ Output The DQ0−DQ31 input and output data are synchronized
with both edges of DQS.
A1,A12,G1,G12
DQS0
−DQS3
Data Strobe
DQS is Bi-directional signal. DQS is input signal during
write operation and output signal during read operation.
It is Edge-aligned with read data, Center-aligned with
write data.
M1
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is ignored
and previous operation continues.
K1,K2,L1
RAS , CAS ,
WE
Command Inputs Command inputs (along with CS ) define the command
being entered.
A2,A11,G2,G11
DM0
−DM3
Write mask
DM is an input mask signal for writes data. When DM is
asserted “high” in burst write, the input data is masked.
DM is synchronized with both edges of DQS.
L10,L11
CLK,
CLK
Differential clock
inputs
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge
of CLK .
M11
CKE
Clock Enable
CKE controls the clock activation and deactivation. CKE
is synchronous for POWER-DOWN entry and exit, and
for SELF REFRESH entry CKE must be maintained high
throughout READ and WRITE accesses. Input buffers,
excluding CLK, CLK and CKE are disabled during
POWER-DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH.
M12
VREF
Reference Voltage VREF is reference voltage for inputs.
C6,C7,D3,D10,K3,K
6, K7,K10
VDD
Power ( +2.5V )
Power for logic circuit inside DDR SDRAM.


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